CCM Clock Gating Register 5
| CG0 | rom clock (rom_clk_enable) |
| CG1 | flexio1 clock (flexio1_clk_enable) |
| CG2 | wdog3 clock (wdog3_clk_enable) |
| CG3 | dma clock (dma_clk_enable) |
| CG4 | kpp clock (kpp_clk_enable) |
| CG5 | wdog2 clock (wdog2_clk_enable) |
| CG6 | aipstz4 clocks (aips_tz4_clk_enable) |
| CG7 | spdif clock (spdif_clk_enable) |
| CG8 | sim_main clock (sim_main_clk_enable) |
| CG9 | sai1 clock (sai1_clk_enable) |
| CG10 | sai2 clock (sai2_clk_enable) |
| CG11 | sai3 clock (sai3_clk_enable) |
| CG12 | lpuart1 clock (lpuart1_clk_enable) |
| CG13 | lpuart7 clock (lpuart7_clk_enable) |
| CG14 | snvs_hp clock (snvs_hp_clk_enable) |
| CG15 | snvs_lp clock (snvs_lp_clk_enable) |